1. Field of the Invention
This invention relates generally to the field of digital interface design and, more particularly, to linear half-rate clock and data recovery (CDR) circuits.
2. Description of the Related Art
Designers usually embed clock information in transmitted data signals to meet greater bandwidth requirements in a reduced area. Information signals including only binary data without separate clock signals (i.e., the clock information is embedded in the data) may require only half the bandwidth for transmission when compared to the bandwidth that may be required to transmit information signals including separate data and clock signals. Since the clock information in data signals is preferably embedded in the data, transceivers typically include clock and data recovery (CDR) circuits to recover the embedded clock information of a received data signal to decode the data. Thus, CDR circuits typically perform critical functions in high-speed transceivers.
CDR circuits may be implemented using phase-locked loops (PLLs). PLLs are usually used in devices to receive a reference clock signal having a constant frequency and derive a local clock that is a fraction of and synchronized with the reference clock. However, CDR circuits are typically designed to recover clock information embedded in a data signal having a variable frequency. In this case, due to the variable frequency of the data signal, CDR circuits that are implemented using PLLs (e.g., digital PLLs) preferably include phase detectors having additional circuitry to continuously determine the phase difference between the received data signal and a local clock signal. The phase difference determined by the phase detector may then be used to change the frequency of the local clock accordingly to align one or both edges of the clock signal with the baud center of the data. When one or both edges of the clock signal are aligned with the baud center of the data, it is typically referred to as a locked condition because the clock signal is locked to the baud center of the data.
FIG. 1A is a block diagram of a CDR circuit 100 implemented using a PLL design. The CDR circuit 100 may include a phase detector 150, a loop filter 160, and a voltage-controlled oscillator (VCO) 170. The phase detector 150 typically receives two input signals: data signal 125 and clock signal 130. The phase detector 150 may determine the phase difference between the data signal 125 and the clock signal 130 to generate a phase error signal 135, which is generally a stream of positive and negative current pulses. The loop filter 160, which typically functions as an integrator, may receive the phase error signal 135 from the phase detector 150 and produce a voltage control signal 140 to drive the VCO 170. The VCO 170 outputs the clock signal 130 having a frequency that is dependent upon the voltage control signal 140.
The CDR circuit 100 may be a full-rate CDR circuit or a half-rate CDR circuit. Typically, the design of the phase detector 150 determines whether the CDR circuit 100 is a full-rate or a half-rate CDR circuit. A full-rate CDR preferably produces a clock signal with an average frequency that is the same as the data rate of the received data signal. A half-rate CDR preferably generates a clock signal with an average frequency that is half the data rate of the received data signal. For example, if the data rate is 2.5 Gbits/sec, then a full-rate CDR may generate a clock signal with an average frequency of 2.5 GHz, and a half-rate CDR may generate a clock signal with an average frequency of 1.25 GHz. Since power consumption is proportional to the square of oscillating frequency of the VCO, a half-rate CDR consumes less power than a full-rate CDR.
FIG. 1B is a timing diagram showing the difference between a locked condition in a full-rate CDR circuit and a locked condition in a half-rate CDR circuit. In a full-rate CDR circuit, a locked condition may be achieved when the rising edge of the full-rate clock signal 130A is aligned with the baud center of the data signal 125. In a half-rate CDR circuit, a locked condition may be achieved when both the rising and falling edges of the half-rate clock signal 130B are aligned with the baud center of data signal 125.
One common design of a full-rate CDR circuit for producing a clock signal that is aligned with the baud center of a data signal is the Hogge CDR circuit. A detailed description of the Hogge CDR is found in an article entitled “A Self-Correcting Clock Recovery Circuit”, IEEE Journal of Lightwave Technology, Vol. LT-3, No. 6, pp. 1312-1314, December 1985, and in U.S. Pat. No. 4,535,459, August 1985, both by Charles R. Hogge, Jr. The Hogge CDR is a linear, compact, and efficient CDR design. However, the major drawbacks to this architecture are that the Hogge CDR is a full-rate CDR and it generates data dependent jitter or noise. Data dependent jitter typically refers to jitter in the phase of the clock signal generated by the VCO due to variations in data density of the receive data signal. More specifically, variations in data density result in inaccurate voltage control signals being sent to the VCO, which may result in variations in the phase of successive pulses of the clock signal generated by the VCO.
The CDR designed by DeVito greatly reduces some of the jitter problems of the Hogge CDR by including a triwave phase detector. A detailed description of this CDR design is found in an article entitled “A Versatile Clock Recovery Architecture and Monolithic Implementation”, in Monolithic Phase-Locked Loops and Clock Recovery Circuits, Theory and Design, B. Razavi, Ed. New York: IEEE Press, 1996, and in U.S. Pat. No. 5,027,085, June 1991, both by Lawrence M. DeVito. A triwave phase detector may yield a CDR design with greatly diminished data dependent jitter. However, the drawbacks to this implementation are that the CDR is a full-rate CDR and it has a greater sensitivity to duty cycle distortion in the clock signal than the Hogge CDR. The greater duty cycle sensitivity is due to the uneven weighting used in the architecture with respect to the exclusive-OR gate outputs.
A solution that improves on the DeVito CDR design is the CDR circuit designed by Lee. A detailed description of this CDR design is found in an article entitled “A 155-MHz Clock Recovery Delay- and Phase-Locked Loop”, IEEE Journal of Solid-State Circuits, Vol. 27, No. 12, pp. 1736-1745, December 1992, by Thomas H. Lee and John F. Bulzacchelli. This CDR circuit preserves the benefits of triwave implementation and reduces the duty cycle sensitivity by providing equal weighting to the different branches at the output of the exclusive-OR gates of the phase detector. The modified triwave phase detector has two distinct down-integration intervals clocked on opposite edges of the clock, rather than a single clock edge multiplied by two. As a consequence, duty cycle effects are attenuated. However, one of the drawbacks of this CDR design is that it is a full-rate CDR.
One common drawback of the linear CDR designs described above is that these CDR circuits are full-rate CDRs; therefore, as describe above, these linear full-rate CDRs consume more power than linear half-rate CDRs.